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KM44S32030
8M x 4Bit x 4 Banks Synchronous DRAM
FEATURES
* JEDEC standard 3.3V power supply * LVTTL compatible with multiplexed address * Four banks operation * MRS cycle with address key programs -. CAS Latency (2 & 3) -. Burst Length (1, 2, 4, 8) -. Burst Type (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock. * Burst Read Single-bit Write operation * DQM for masking * Auto & self refresh * 64ms refresh period (4K cycle)
Preliminary CMOS SDRAM
GENERAL DESCRIPTION
The KM44S32030 is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clcok cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part NO. KM44S32030T-G/F8 KM44S32030T-G/FH KM44S32030T-G/FL KM44S32030T-G/F10 MAX Freq. 125MHz 100MHz 100MHz 100MHz LVTTL 54pin TSOP(II) Interface Package
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select 8M x 4 Sense AMP 8M x 4 8M x 4 8M x 4 Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer Latency & Burst Length
LRAS
LCBR
LCKE LRAS LCBR LWE LCAS
Programming Register LWCBR LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM * Samsung Electronics reserves the right to change products or specification without notice.
REV. 2 Mar. '98
KM44S32030
PIN CONFIGURATION (TOP VIEW)
VDD N.C VDDQ N.C DQ0 VSSQ N.C N.C VDDQ N.C DQ1 VSSQ N.C VDD N.C WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS N.C VSSQ N.C DQ3 VDDQ N.C N.C VSSQ N.C DQ2 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS
Preliminary CMOS SDRAM
54PIN TSOP (II) (400mil x 875mil) (0.8 mm PIN PITCH)
PIN FUNCTION DESCRIPTION
PIN CLK CS NAME System Clock Chip Select INPUT FUNCTION Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row / column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, column address : CA0 ~ CA9, CA11 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device.
CKE
Clock Enable
A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM DQ0 ~ 3 VDD/VSS VDDQ/VSSQ N.C/RFU
Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection/ Reserved for Future Use
REV. 2 Mar. '98
KM44S32030
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50
Preliminary CMOS SDRAM
Unit V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input logic high votlage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current(Inputs) Input leakage current (I/O pins) Symbol VDD, VDDQ VIH VIL VOH VOL IIL IIL Min 3.0 2.0 -0.3 2.4 -5 -5 Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 5 5 Unit V V V V V uA uA 1 2 IOH = -2mA IOL = 2mA 3 3,4 Note
Note : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ, Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V VOUT VDDQ.
CAPACITANCE
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) Symbol CCLK CIN CADD COUT Min 2.5 2.5 2.5 4 Max 4 5 5 6.5 Unit pF pF pF pF
Parameter Clock RAS, CAS, WE, CS, CKE, DQM Address DQ0 ~ DQ3
REV. 2 Mar. '98
KM44S32030
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Symbol Test Condition Burst Length =1 tRC tRC(min) IOL = 0 mA CKE VIL(max), tCC = 15ns CKE & CLK VIL(max), tCC = CKE VIH(min),CS VIH(min),tCC=15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 15ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns. CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IOL = 0 mA Page Burst tCCD = 2CLKs tRC tRC(min) CKE 0.2V 3 2 140 105 CAS Latency
Preliminary CMOS SDRAM
Version -8 120 -H 110 1 1 15 -L 110 -10 105
Unit
Note
Operating Current (One Bank Active) Precharge Standby Current in power-down mode
ICC1 ICC2P ICC2PS ICC2N
mA
1
mA
Precharge Standby Current in non power-down mode ICC2NS Active Standby Current in power-down mode ICC3P ICC3PS ICC3N
mA 7 5 5 30 mA
mA
Active Standby Current in non power-down mode (One Bank Active)
ICC3NS
20 115 115 200 1 600 115 105 115 105 165
mA
Operating Current (Burst Mode) Refresh Current Self Refresh Current
ICC4 ICC5 ICC6
mA mA mA uA
1 2 3 4
Note : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. KM44S32030T-G** 4. KM44S32030T-F**
REV. 2 Mar. '98
KM44S32030
AC OPERATING TEST CONDITIONS
Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
3.3V
Preliminary CMOS SDRAM
(VDD = 3.3V 0.3V, TA = 0 to 70C) Value 2.4 / 0.4 1.4 tr / tf = 1 / 1 1.4 See Fig. 2
Vtt=1.4V
Unit V V ns V
1200 Output 870 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0=50
50
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol -8 tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tCDL(min) tBDL(min) tCCD(min) 68 8 70 10 1 1 1 2 1 16 20 20 48 -H 20 20 20 50 100 70 10 80 12 Version -L 20 20 20 50 -10 20 24 24 50 ns ns ns ns us ns ns CLK CLK CLK ea 1 2 2 2 3 4 1 1 1 1 Unit Note
CAS latency=3 CAS latency=2
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.
REV. 2 Mar. '98
KM44S32030
AC CHARACTERISTICS
Parameter CAS latency=3 CAS latency=2 CLK to valid output delay Output data hold time CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 3 3 3 3 2 1 1 6 6 tSAC (AC operating conditions unless otherwise noted) Symbol Min CLK cycle time tCC 8 12 6 6 3 3 3 3 2 1 1 6 6 -8 Max 1000 Min 10 10 6 6 3 3 3 3 2 1 1 6 7 -H Max 1000 Min 10 12 6 7 3 3 -L Max 1000
Preliminary CMOS SDRAM
-10 Min 10 13 7 7 ns ns ns ns ns ns 7 7 ns 2 3 3 3 3 2 ns 1, 2 Max 1000 ns 1
Unit
Note
CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2
3.5 3.5 2.5 1.5 1
Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
REV. 2 Mar. '98
KM44S32030
IBIS Specification
IOH Characteristics(Pull-up)
Voltage (V) 3.45 3.3 3 2.6 2.4 2 1.8 1.65 1.5 1.4 1 0 100Mhz min I(mA) 100Mhz max I(mA) -2.4 -27.3 -74.1 -129.2 -153.3 -197 -226.2 -248 -269.7 -284.3 -344.5 -502.4 66Mhz min I(mA) 0 0 -100 -200 ma -300 -400 -500 -600 voltage
Ioh min(100Mhz) Ioh min(66Mhz)
Preliminary CMOS SDRAM
66Mhz and 100Mhz Pull-Up 0.5 1 1.5 2 2.5 3 3.5
0 -21.1 -34.1 -58.7 -67.3 -73 -77.9 -80.8 -88.6 -93
-0.7 -7.5 -13.3 -27.5 -35.5 -41.1 -47.9 -52.4 -72.5 -93
Ioh max(66 and 100Mhz)
66Mhz and 100Mhz Pull-Down
IOL Characteristics(Pull-Down)
Voltage (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3 3.45 100Mhz min I(mA) 0.0 27.5 41.8 51.6 58.0 70.7 72.9 75.4 77.0 77.6 80.3 81.4 100Mhz max I(mA) 0.0 70.2 107.5 133.8 151.2 187.7 194.4 202.5 208.6 212.0 219.6 222.6 66Mhz min I(mA) 0.0 17.7 26.9 33.3 37.6 46.6 48.0 49.5 50.7 51.5 54.2 54.9
250
200
150 ma 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5
voltage
Iol min(100Mhz) Iol min(66Mhz) Iol max(100Mhz)
REV. 2 Mar. '98
KM44S32030
Preliminary CMOS SDRAM
Minimum VDD Clamp Current (referenced to VDD) 20
VDD Clamp @CLK,CKE, CS,DQM & DQ
VDD 0.0V 0.2V 0.4V 0.6V 0.7V 0.8V 0.9V 1.0V 1.2V 1.4V 1.6V 1.8V 2.0V 2.2V 2.4V 2.6V I(mA) 0.0mA 0.0mA 0.0mA 0.0mA 0.0mA 0.0mA 0.0mA 0.23mA 1.34mA 3.02mA 5.06mA 7.35mA 9.83mA 12.48mA 15.30mA 18.31mA
15
I(ma)
10
5
0 0 1 Voltage
I(ma)
2
3
Minimum VSS Clamp Current
VSS Clamp @CLK,CKE, CS,DQM & DQ
VSS -2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2 0.0 I(mA) -57.23mA -45.77mA -38.26mA -31.22mA -24.58mA -18.37mA -12.56mA -7.57mA -3.37mA -1.75mA -0.58mA -0.05mA 0.0mA 0.0mA 0.0mA 0.0mA 0 -10 -20 I(ma) -30 -40 -50 -60
-3
-2
-1
0
Voltage
I(ma)
REV. 2 Mar. '98
KM44S32030
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE
KM44S32030T-8
Frequency 125MHz (8.0ns) 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) CAS Latency 3 3 2 2 2 tRC 68ns 9 7 6 6 5 tRAS 48ns 6 5 4 4 4 tRP 20ns 3 2 2 2 2 tRRD 16ns 2 2 2 2 2 tRCD 20ns 3 2 2 2 2 tCCD 8ns 1 1 1 1 1
Preliminary CMOS SDRAM
(Unit : number of clock) tCDL 8ns 1 1 1 1 1 tRDL 8ns 1 1 1 1 1
KM44S32030T-H
Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) CAS Latency 2 2 2 2 2 tRC 70ns 7 6 6 5 5 tRAS 50ns 5 5 4 4 3 tRP 20ns 2 2 2 2 2 tRRD 20ns 2 2 2 2 2 tRCD 20ns 2 2 2 2 2 tCCD 10ns 1 1 1 1 1
(Unit : number of clock) tCDL 10ns 1 1 1 1 1 tRDL 10ns 1 1 1 1 1
KM44S32030T-L
Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) CAS Latency 3 2 2 2 2 tRC 70ns 7 6 6 5 5 tRAS 50ns 5 5 4 4 3 tRP 20ns 2 2 2 2 2 tRRD 20ns 2 2 2 2 2 tRCD 20ns 2 2 2 2 2 tCCD 10ns 1 1 1 1 1
(Unit : number of clock) tCDL 10ns 1 1 1 1 1 tRDL 10ns 1 1 1 1 1
KM44S32030T-10
Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) CAS Latency 3 3 2 2 2 tRC 80ns 8 7 7 6 5 tRAS 50ns 5 5 4 4 3 tRP 24ns 3 2 2 2 2 tRRD 20ns 2 2 2 2 2 tRCD 24ns 3 2 2 2 2 tCCD 10ns 1 1 1 1 1
(Unit : number of clock) tCDL 10ns 1 1 1 1 1 tRDL 12ns 2 1 1 1 1
REV. 2 Mar. '98
KM44S32030
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit L H H
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1
Preliminary CMOS SDRAM
A11, A9 ~ A0
A10/AP
Note
H H
X H L H X X
L L L H
L L H X L H
L L H X H L
L H H X H H
X X
OP CODE X
1, 2 3 3
X X X V V
X Row Address L H
Column Address (A0~A9,A11) Column Address (A0~A9,A11)
3 3
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Clock Suspend or Active Power Down Entry Exit Entry Precharge Power Down Mode Exit DQM No Operation Command Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
L L
4 4, 5 4 4, 5 6
H H H
X X X
L L L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
L H X
V X
L H
X
H L H
L H L
X X X X X X V X X 7
X H L
L H H
H
H L
X
H L
X H
X H
X H
X
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low) Note : 1. OP Code : Operand Code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the assoiated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
REV. 2 Mar. '98

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